The present invention relates to circuitry for verifying the contents of a group of memory cells, such as Electrically Erasable Programmable Read Only Memory (EEPROM) cells. The invention is in particular applicable to programmable logic devices that are configured through the use of EEPROM cells.
A programmable logic device (PLD) is a programmable integrated circuit that allows the user of the circuit, using software control, to customize the logic functions the circuit will perform. The logic functions previously performed by small, medium and large scale integration integrated circuits can instead be performed by programmable logic devices. When a typical programmable logic device is supplied by an integrated circuit manufacturer, it is not yet capable of performing any specific function. The user, in conjunction with software supplied by the programmable logic device manufacturer, can program the PLD to perform the specific function or functions required by the user's application. The PLD then can function in a larger system designed by the user, just as though dedicated logic chips were employed.
A typical PLD consists of an array of logic cells that can be individually programmed and arbitrarily interconnected to each other to provide internal input and output signals, thus permitting the performance of highly complex combinational and sequential logic functions. The program is implemented in the PLD by setting the states of programmable elements, such as EEPROM cells, associated with each logic cell. After programming the EEPROM cells, it is useful to have the ability to verify the contents of the memory cells to ensure that the logic cell will be configured as desired.
It is known in the prior art to verify the contents of the EEPROM cells with a verification circuit including a number of NMOS transistors connected in series. Each NMOS transistor acts as a pass transistor for its associated EEPROM cell, allowing the user to test each EEPROM cell individually to determine whether or not it has been programmed as desired. However, when a number of NMOS transistors are connected in series, the device size of each transistor must increase as the number of transistors in the verify path increases. Thus, the verification circuitry occupies more and more space on the PLD chip as the number of EEPROM cells, and NMOS verification transistors, increases.
Additionally, because the device size of each NMOS transistor grows nearly linearly with each additional transistor connected in series, it is preferable to divide all the EEPROM bits associated with one logic cell in a PLD into a number of groups, creating a separate verification path for each group of EEPROM bits. While this helps control the device size of each verify transistor by minimizing the number connected in series, it adds to the complexity of the logic in the PLD by adding multiple verification paths for the EEPROM bits associated with a logic cell. Accordingly, it would be preferable to design a verification path for EEPROM cells that occupies less space on the chip die and that does not increase the complexity of logic in the PLD.